Difference between revisions of "Multi-threshold CMOS"

Latest revision as of 13:50, 10 December 2011

Multi-threshold CMOS (MTCMOS) utilized transistors with multiple threshold voltages (Vt) to optimize delay or power. Lower voltage devices are used on critical delay paths to minimize clock periods. Higher voltage devices are used on non-critical paths to reduce static leakage power without incurring a delay penalty. Typical high voltage devices reduce static leakage by 10 times compared with low voltage devices. One method of creating devices with multiple threshold voltages is to apply different bias voltages (Vb) to the base or bulk terminal of transistors, the other way can be "gate engineering". In MOSFET devices, lower bias voltages will increase voltages, increase delay, and reduce static leakage.

A common MTCMOS approach for reducing power uses sleep transistors. Logic is supplied by a virtual power rail. Low voltage devices are used in the logic for speed. The logic may be turned off by collapsing the virtual power rail. High voltage devices connecting the power rails and virtual power rails are turned off in sleep mode. High voltage devices are used as sleep transistors to reduce static leakage.

The design of the power switch which turns on and off the power supply to the logic gates is essential to low-voltage high-speed circuit techniques such as multi-threshold voltage CMOS (MTCMOS). This is because this switch influences the speed, area, and power of a low-voltage LSI.