Lookahead Carry Unit
A Lookahead Carry Unit (LCU) is a logical unit in digital circuit design used to decrease calculation time in adder units and used in conjunction with carry look-ahead adders (CLAs).
4-bit adder
A single 4-bit CLA is shown below:
16-bit adder
By combining four 4-bit CLAs, a 16-bit adder can be created but additional logic is needed in the form of an LCU.
The LCU accepts the group propagate (<math>P_G</math>) and group generate (<math>G_G</math>) from each of the four CLAs. <math>P_G</math> and <math>G_G</math> have the following expressions for each CLA adder:[1]
- <math>P_G = P_3 \cdot P_2 \cdot P_1 \cdot P_0</math>
- <math>G_G = G_3 + P_3 \cdot G_2 + P_3 \cdot P_2 \cdot G_1 + P_3 \cdot P_2 \cdot P_1 \cdot G_0</math>
The LCU then generates the carry input for each CLA.
Assume that <math>P_i</math> is <math>P_G</math> and <math>G_i</math> is <math>G_G</math> from the ith CLA then the output carry bits are
- <math>C_{4} = G_0 + P_0 \cdot C_0</math>
- <math>C_{8} = G_{4} + P_{4} \cdot C_{4}</math>
- <math>C_{12} = G_{8} + P_{8} \cdot C_{8}</math>
- <math>C_{16} = G_{12} + P_{12} \cdot C_{12}</math>
Substituting <math>C_{4}</math> into <math>C_{8}</math>, then <math>C_{8}</math> into <math>C_{12}</math>, then <math>C_{12}</math> into <math>C_{16}</math> yields the expanded equations:
- <math>C_{4} = G_0 + P_0 \cdot C_0</math>
- <math>C_{8} = G_4 + G_0 \cdot P_4 + C_0 \cdot P_0 \cdot P_4</math>
- <math>C_{12} = G_8 + G_4 \cdot P_8 + G_0 \cdot P_4 \cdot P_8 + C_0 \cdot P_0 \cdot P_4 \cdot P_8</math>
- <math>C_{16} = G_{12} + G_8 \cdot P_{12} + G_4 \cdot P_8 \cdot P_{12} + G_0 \cdot P_4 \cdot P_8 \cdot P_{12} + C_0 \cdot P_0 \cdot P_4 \cdot P_8 \cdot P_{12}</math>
<math>C_{4}</math> corresponds to the carry input into the second CLA; <math>C_{8}</math> to the third CLA; <math>C{12}</math> to the fourth CLA; and <math>C_{16}</math> to overflow carry bit.
In addition, the LCU can calculate its own propagate and generate:
- <math>P_{LCU} = P_0 \cdot P_4 \cdot P_8 \cdot P_{12}</math>
- <math>G_{LCU} = G_{12} + G_8 \cdot P_{12} + G_4 \cdot P_8 \cdot P_{12} + G_0 \cdot P_4 \cdot P_8 \cdot P_{12} + C_0 \cdot P_0 \cdot P_4 \cdot P_8 \cdot P_{12} = C_{16}</math>
64-bit adder
By combining 4 CLAs and an LCU together creates a 16-bit adder. Four of these units can be combined to form a 64-bit adder. An additional (second-level) LCU is needed that accepts the propagate (<math>P_{LCU}</math>) and generate (<math>G_{LCU}</math>) from each LCU and the four carry outputs generated by the second-level LCU are fed into the first-level LCUs.
References
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<references />, or <references group="..." />- Katz, Randy (1994). Contemporary Logic Design. The Benjamin/Cummings Publishing Company. pp. 249–256. ISBN 0-8053-2703-7.
- Vahid, Frank (2006). Digital Design. John Wiley and Sons Publishers. pp. 296–316. ISBN 0470044373.de:Paralleladdierer_mit_Übertragsvorausberechnung
