Current mode logic

Current mode logic (CML), or source-coupled logic (SCL), is a differential digital logic family intended to transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s over a standard printed circuit board.

File:CML line.svg

CML termination scheme

The transmission is point-to-point, unidirectional and is usually terminated at the destination with 50 Ω resistors to V_cc on both differential lines. CML is the physical layer used in DVI and HDMI video links, and is frequently used in interfaces to fiber optic components.

This technology has been also used in design of high speed integrated circuits such as in telecommunication applications (serial data transceivers, frequency synthesizers, etc.). This fast operation of CML circuits is mainly due to their lower output voltage swing compared to the static CMOS circuits and also the very fast current switching taking place at the input differential pair circuit.

References

• System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 – 3.125 Gbit/s Parallel Interfaces. OIF, October 2002.
• TFI-5: TDM Fabric to Framer Interface Implementation Agreement. OIF, September 16, 2003
• Introduction to LVDS, PECL, and CML, Maxim, http://pdfserv.maxim-ic.com/en/an/AN291.pdf
• http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=ee685:start
• Interfacing between LVPECL, VML, cml and LVDS Levels, http://focus.ti.com/lit/an/slla120/slla120.pdf