Address decoder
In digital electronics, an address decoder is a decoder circuit that has two or more bits of an address bus as inputs and that has one or more device selection lines as outputs.[1] When the address for a particular device appears on the address bus, the address decoder asserts the selection line for that device. A separate single-device address decoder may be incorporated into each device on an address bus, or a single address decoder may serve multiple devices.[2] When a single address decoder serves multiple devices, an address decoder with n address input bits can serve up to 2n separate devices. Several members of the 7400 series of integrated circuit are address decoders. An example is the 74154.[3] This address decoder has four address inputs and sixteen (i.e., 24 ) device selector outputs. An address decoder is also referred to as a "demultiplexer" or "demux," although these terms are more general and can refer to devices other than address decoders. The 74154 mentioned above can be called a "4-to-16 demux."
Address decoders are fundamental building blocks for systems that use buses. They are represented in all integrated circuit families and processes and in all standard FPGA and ASIC libraries. They are discussed in introductory textbooks in digital logic design.[1]
References
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- ↑ 1.0 1.1 Paul Horowitz and Winfield Hill (1989). The Art of Electronics (2nd ed.). Cambridge University Press. p. 685,766. ISBN 978-0-521-37095-0.
- ↑ S. J. Cahill (1993). Digital and microprocessor engineering (2nd ed.). Ellis Horwood. pp. 489–494. ISBN 978-0-13-213398-2.
- ↑ Datasheet for 74HC154
