Time to digital converter
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In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for converting a signal of sporadic pulses into a digital representation of their time indices. In other words, a TDC outputs the time of arrival for each incoming pulse. Because the magnitudes of the pulses are not usually measured, a TDC is used when the important information is to be found in the timing of events. In practice, a TDC usually follows a discriminator. TDCs are most often used in applications where measurement events happen infrequently, such as high energy physics experiments, where the sheer number of data channels in most detectors ensures that each channel will be excited only infrequently by particles such as electrons, photons, and ions.
In its simplest implementation, a TDC is simply a high-frequency counter with a buffered output.
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Implementation
Typically a TDC has a crystal oscillator, which has good long term stability, but oscillates too slowly (80 MHz in 2007). A faster overtone crystal oscillator or a SAW oscillator could be used for the reference, but the TDC also has a VCO for the ultimate frequency needed. To be fast this is a loop of transistors (series of logic gates, namely inverters). This also acts as a Johnson counter, which divides this frequency down to a slow frequency. A phase-locked loop is used to lock this low frequency to the frequency of the crystal oscillator. A slow synchronous counter, counts the slow oscillations.
For every stop pulse a copy of the timer is stored. Some TDCs start the counter after a start pulse and stop after a stop pulse. But this is incompatible with the TDC and allows only one stop pulse.
The speed of counters fabricated in CMOS-technology is limited by the capacity between the gate and the channel and by the resistance of the channel and the signal traces. The product of both is the cut-off-frequency. Modern chip technology allows multiple metal layers and therefore coils with a large number of windings to be inserted into the chip. This allows to peak the device for a specific frequency, which may lie well above the cut-off-frequency of the original transistor. The counter is then called a prescaler. The frequency of the voltage-controlled oscillator, for which the use of a coil is more common, has to be matched to the prescaler. A peaked variant of the Johnson counter is the traveling-wave counter which also achieves sub-cycle resolution. Other methods to achieve sub-cycle resolution include analog-to-digital converters and vernier Johnson counters.
Delay generator
This is a digital to time converter. Whereas the TDC measures the time between a start and a stop pulse, the delay generator gets a start pulse at its inputs, then counts down and outputs a stop pulse. For low jitter the synchronous counter has to feed a zero flag from the most significant bit down to the least significant bit and then combine it with the output from the Johnson counter.
A digital-to-analog converter (DAC) could be used to achieve sub-cycle resolution, but it is easier to either use vernier Johnson counters or traveling-wave Johnson counters.
The delay generator can be used for pulse width modulation, e.g. to drive a MOSFET to load a Pockels cell within 8 ns with a specific charge.
The output of a delay generator can gate a digital-to-analog converter and so pulses of a variable height can be generated. This allows matching to low levels needed by analog electronics, higher levels for ECL and even higher levels for TTL. If a series of DACs is gated in sequence, variable pulse shapes can be generated to account for any transfer function.
Discriminator
Even if the input is binary, after sampling with the oscillator signal the signal is analog (due to the finite edge width). Therefore an analog-to-digital converter is always employed after the sampler, the same is true for a simple comparator which can be implemented as a cascade of differential amplifiers, where the latter stages are driven into saturation, that means either into the low or the high state (1-bit ADC). At every leading edge of the time-discrete and voltage-discrete signal the time is fed into the FIFO.
Constant fraction discriminator
As a TDC is mainly a logic device and has problems with voltages between low and high state. A constant fraction discriminator differentiates a copy of the input signal. A look at Fourier transformation shows, that this can be accomplished by a 90° phase shift for all frequency components. Omitting the 1/f has some benefits. This signal is fed into a second comparator to get the maximum. At the end the signals of both comparators is send into an AND gate. A constant fraction discriminator reduces jitter when the single particles produce short pulses of different height and the measurement device blurs them into long pulses with a constant shape.
Utilities
A flip flop can be used to convert pulses into edges and vice versa.
A gate has an analog and a logic input. When the logic input is low, the output is zero. A typical sampling pulse of 1 ns width and a 1Msamples ADC and a signal-to-noise ratio of 100 means that the analog signal has to be suppressed by a factor of 100000 (low leakage). If the gate is used in conjunction with an integrator, the transmission should be constant over the integration interval within 0.001.
In a sampling oscilloscope an edge of a signal is sharpened by a diode pair, then fed through a delay generator, then converted into a pulse, and then gates the signal. The output of the gate is held in a capacitor and converted by an ADC. A multi-channel analyzer derives the gate pulse from a const-fraction discriminator and uses a fixed delay for a third copy of the original signal to account for the delay in the discriminator. If a series of gates is opened in a short sequence, the pulse shape can be sampled. No const-fraction discriminator is needed then and the system is very flexible concerning the pulse shape.
Often the sampled charge could be stored in the capacitor formed by the gate and channel of a MOSFET. The any current drawn by the ADC will not reduce the charge. Furthermore by drawing the current a long time a large charge amplification is possible. This is called a sample and hold circuit or also a track and hold circuit. The binary variant is called a buffer.
